Abstracts of invited talks SHARCS'06
- Jens Franke (Rheinische Friedrich-Wilhelms Universität
Bonn)
On the factorization of RSA200
Abstract:
We present some data for the factorizations RSA200 and RSA640 by the
general number field sieve. We will also discuss the perspectives for
larger projects.
- Kris Gaj (George Mason University )
Implementing the Elliptic Curve Method of Factoring in
Reconfigurable Hardware
Abstract:
A novel portable hardware architecture of the Elliptic Curve Method of
factoring, designed and optimized for the application in the relation
collection step of the Number Field Sieve is described and analyzed. A
timing comparison to optimized software implementations is presented,
as well as a comparison in terms of the product of cost and time among
the FPGA, ASIC, and microprocessor technologies. We discuss state of
the art general-purpose high-performance reconfigurable computers,
their programming environments, and the vendor and user libraries
suitable for cryptanalysis, together with our plans for porting ECM to
selected reconfigurable computers.
- Alan Gara (BlueGene System Architect, IBM)
BlueGene/L: An overview and exploration into unique architectural
features that can be exploited for cryptanalysis
Abstract:
The BlueGene/L supercomputer is currently first in terms of the
Top500 supercomputer list with a peak performance of 360 teraflops. In
this talk the BlueGene/L architecture will be described and several
novel features of the architecture that are not typically discussed in
the high performance computing arena will be explored. These features
involve hardware assist for global operations such as sorting and
broadcast over arbitrary machine sizes. Benchmark results and
performance estimates will be given for various global operations not
commonly encountered in high performance computing but which may be of
value for cryptanalysis.
- Yusuf Leblebici (École Polytechnique Fédérale
de Lausanne)
How Much Faster Can We Go? : A Technology Outlook
Abstract:
The computational capabilities of special-purpose hardware
designed for cryptanalysis are mainly determined by the
chosen architecture, as well as the physical capabilities
of devices and circuits that are used to implemement this
architecture. The overall performance of digital circuits,
in turn, is a strong function of technology scaling which
enabled the successful continuation of "Moore's Law" over
more than three decades. Our ability to build sufficiently
powerful hardware solutions for cryptanalysis will depend
on how we can further exploit technology scaling, and what
the fundamental limitations are. In this talk, we will
review the current and near-term status of developments
in device technologies; the prospects of CMOS and other
technologies (especially nano-scale devices) to succeed
in tera-transistor systems; the status of photonic devices
and optoelectronics; potentially problematic issues such as
clock distribution, reliability and power density; and the
fundamental limits imposed on irreversible von Neumann
computing machines through Boltzmann statistics and
Heisenberg relations.